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q_sys
- PCIe ip核。使用Quartus II 11.0，在Altera开发板4cgx15上验证通过。-PCIe ip core. Using the Quartus II 11.0, in the Altera development board 4cgx15 verify through.
unishift
- An universal shift register performs the following tasks load, right shift ,left shift and parallel load as the selection inputs are 00,01,10,11 respectively. Such a register is implemented here in Quartus.
QII_11.0_SP1_Linux
- un crack pra quartus II 11.0 sp1
exp_micro_s
- 自己在QuartusII9.1及Modelsim新版本中完成的microsequencer实例的工程文件。 1.echo uart,接收rx_data,再回复！ 2.运行时请注意完整路径： D:\EXP\EXP_SOPCbuilder\exp_micro_s 3.UART数据输入问题？ 3.1 MODELSIM中w完信号后，run/restart一次。 3.2 设置clock=20ns。 3.3 命令行中输入uart_drive调出uart_
sopc_lcd_led
- 利用De0_nano建立的SOPC系统，其中包含有LCD，LED，DDS函数发生和ADC等源程序。工程编译环境为Quartus II 11.0，eclipse for sopc。-Established by De0_nano SOPC system, which includes LCD, LED, DDS functions occurrence and ADC and other source. Project build environment for the Quartus II 11
counter10
- verilog编写的10进制计数器，并且功能仿真正确。软件为quartus II 11.0,和Modelsim-verilog prepared 10 binary counter, and functional simulation is correct. Software quartus II 11.0, and Modelsim
EP2C8-2010_FPGA
- EP2C208C8 FPGA开发源代码（芯蓝C8板） turn_on_led 点亮LED sw_led 拨动开关控制LED rider_led 跑马灯 water_led 流水灯 key_led_without_debounce 轻触开关控制LED，无按键去抖 key_led_with_debounce 轻触开关控制LED，有按键去抖 seg7x8_dynamic_disp 七段数码管动态显示 matrixKeyb
IIC_write_one_bite_read_random
- 本实验通过IIC协议完成对EEPROM的操控，进行单字节的写入和随机的读取。-Module Name : IIC通信实验 //Engineer : WHN //Target Versions : EP2C8Q208C8 //Create Date : Quartus II 11.0 //Revision : V1.0 //Descr iption : 本实验通过IIC协议完成对EEPROM的操控，进行单字节的 // 的写入和随机的读取。下面是顶层
ex1
- 设计一个循环灯控制器，该控制器控制红、绿、黄三个发光管循环发亮。要求红发光管亮2秒，绿发光管亮3秒，黄发光管亮1秒。（假设外部提供频率为1MHz的方波信号） 编程环境为Quartus II 11.0 仿真环境为 Modelsim 6.6d 通过仿真可以看出。系统复位后，红发光管亮2秒，绿发光管亮3秒，黄发光管亮1秒，三个发光管循环发亮。 -Design a loop lamp controller that controls the red, green and ye
NRZ_M
- 在quartus II 11.0中，完成对NRZ码的码型变换为NRZ_M码-Completion of the NRZ code pattern transformation NRZ_M code
license
- quartus license -quartus 11.0 license
11
- 介绍了应用FPGA芯片和硬件描述语言(VHDL)设计微波炉控制器系统的方法。系统使用VHDL编程实现各底层模块的功能，顶层的设计采用图形输入完成。论文主要阐述模块化设计的思想和状态图的描述方法，以及他们在硬件描述语言中的应用，并展示了其在Quartus II 开发系统下的仿真结果。-This paper introduces the application of FPGA chip and the hardware descr iption language (VHDL) method for
Quartus-II-11.0
- Crack for Quartus II v11 Confirmed that works
comparator
- FPGA比较器源码编写，适合初学者参考用,用ALTERA的QUARTUS 11.0编译-Compare FPGA source code written for beginners reference, compiled by ALTERA s QUARTUS 11.0
i2c_master
- This details an I2C master component for single master buses, written in VHDL for use in CPLDs and FPGAs. The component reads and writes to user logic over a parallel interface. It was designed using Quartus II, version 11.1. -This details an I2C mas
UART
- 基于quartus ii 11.0与nios ii 11.0 串口通信-Serial communication based on II quartus 11 and II NIOS 11
Quartus-II-11.0.208-SP1-Altera-Complete-Design-Su
- Altera Quartus 12.1 Software Patch
shift
- shift of code VDHL by using quartus -shift of code VDHL by using quartus 11
sys_cpt
- quartus 11.0 破解文件，可用于32位quartus 11.0 破解文件(Quartus 11 crack file, can be used for 32 bit quartus 11 cracked file)